VHDL code for D Flip-Flop

Q. How do I write VHDL code for D Flip Flop
Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff1 is
Port ( data_in : in  STD_LOGIC;
clock : in  STD_LOGIC;
data_out : out  STD_LOGIC);
end dff1;
architecture Behavioral of dff1 is
begin
process(data_in,clock)
begin
if(clock='1' and clock'event)
then
data_out<=data_in;
end if;