VHDL Code For MUX(4:1)

Q. How do I write VHDL code for Multiplexer
Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux1 is
Port ( I0 : in  STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
Y : out STD_LOGIC);
end mux1;
architecture Behavioral of mux1 is
begin
process(I0,I1,I2,I3,S0,S1)
begin