Write a VHDL Code For S-R Flip-Flop

Q. How do I write VHDL code for SR Flip-Flop
Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sr is
Port ( s,r,clk : in STD_LOGIC;
q,qbar,z : inout STD_LOGIC);
end sr;
architecture Behavioral of sr is
begin
process(clk)
begin
if clk='1' then
z<=s or ((not r) and q);
q<=z after 5ns;
qbar<=not z after 5ns;
end if;
end process