VHDL Code for Parallel-Adder

Q. How do I write VHDL code for Parallel Adder
Ans:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pa1 is
Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0);
c : out STD_LOGIC;
cin : in STD_LOGIC);
end pa1;
architecture Behavioral of pa1 is
begin
process(a,b,