Cache Miss : When the address from which the processor wants to read or write is not present in the cache, the same has to be fetched from the main memory. This is termed as cache miss.
Due to a cache miss the processor has to wait for longer time for data as it has to be fetched from the main memory, this time is termed as Miss Penalty.
Miss penalty = "Time to look up in cache" + "Time to fetch from the main memory".
More details about the working of cache is given in
The cache misses as classified into three categories
1. Compulsory Misses
2. Conflict Misses
3. Capacity Misses
Compulsory Misses:
When the system is turned on, the cache does not have any valid data in it and hence the first few reads and writes will always miss in the cache. These misses are termed as compulsory misses as they will always occur when a system turns on.
The figure below describes the same.
Conflict Misses :
Let us take the example of a direct mapped cache . In a direct mapped cache the main memory address can be mapped only to a specific block in the cache. As the main memory will always be bigger in size than the cache, multiple memory addresses can be mapped to one cache block. For e.g. : If we have 32 Bytes of main memory and 8 bytes of cache,each block being 1 byte. Block0,Block8,Block16,Block24 of main memory will all be mapped to Block0 of the cache. If Block0 of main memory is cached and the processor wants to read Block8 of main memory, then the Block8 will have to be moved into the cache, removing Block0 from cache. If processor wants to read Block0 again, it will be a miss as it was replaced by Block8. Thus because of the conflict between Block0 and Block1 leads to the cache misses, hence these types of misses are termed as conflict misses.
The figure below explains the same.
Higher associative can reduce the conflict misses. For e.g.: If the same cache above was a 2 way set associative cache, then both Block0 and Block8 would map o set0 which would have two blocks in it and hence both block0 and block8 could have been cached.
Capacity Misses:
When all the blocks in a cache are occupied any new data that will be needed will always lead to a miss as there is no place to store the data and
the new data will replace some of the old block thus keeping the cache full. The same is depicted in the figure below.
Capacity misses can be reduced by a larger cache size as bigger the cache, longer it would take to fill it up completely.
Due to a cache miss the processor has to wait for longer time for data as it has to be fetched from the main memory, this time is termed as Miss Penalty.
Miss penalty = "Time to look up in cache" + "Time to fetch from the main memory".
More details about the working of cache is given in
The cache misses as classified into three categories
1. Compulsory Misses
2. Conflict Misses
3. Capacity Misses
Compulsory Misses:
When the system is turned on, the cache does not have any valid data in it and hence the first few reads and writes will always miss in the cache. These misses are termed as compulsory misses as they will always occur when a system turns on.
The figure below describes the same.
Conflict Misses :
Let us take the example of a direct mapped cache . In a direct mapped cache the main memory address can be mapped only to a specific block in the cache. As the main memory will always be bigger in size than the cache, multiple memory addresses can be mapped to one cache block. For e.g. : If we have 32 Bytes of main memory and 8 bytes of cache,each block being 1 byte. Block0,Block8,Block16,Block24 of main memory will all be mapped to Block0 of the cache. If Block0 of main memory is cached and the processor wants to read Block8 of main memory, then the Block8 will have to be moved into the cache, removing Block0 from cache. If processor wants to read Block0 again, it will be a miss as it was replaced by Block8. Thus because of the conflict between Block0 and Block1 leads to the cache misses, hence these types of misses are termed as conflict misses.
The figure below explains the same.
Higher associative can reduce the conflict misses. For e.g.: If the same cache above was a 2 way set associative cache, then both Block0 and Block8 would map o set0 which would have two blocks in it and hence both block0 and block8 could have been cached.
Capacity Misses:
When all the blocks in a cache are occupied any new data that will be needed will always lead to a miss as there is no place to store the data and
the new data will replace some of the old block thus keeping the cache full. The same is depicted in the figure below.
Capacity misses can be reduced by a larger cache size as bigger the cache, longer it would take to fill it up completely.
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